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NCP1910
ELECTRICAL CHARACTERISTICS (For typical values T J = 25 ° C, for min/max values T J = ? 40 ° C to +125 ° C, Max T J = 150 ° C,
V CC = 12 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
COMMON TO BOTH CONTROLLERS
SUPPLY SECTION
I CC4
I CC5
I CC6
I CC7
IC consumption, both PFC and LLC loaded in no load conditions
(PFC is 65 kHz and R t = 70 k W (LLC is 25 kHz))
IC consumption, both PFC and LLC loaded 1 nF load conditions
(PFC is 65 kHz and R t = 70 k W (LLC is 25 kHz))
IC consumption in fault mode from V boot (drivers disabled, V boot >
V boot(min) )
IC consumption in OFF mode from V CC (on/off pin is open)
19
19
19
19
?
?
?
?
5.9
6.9
64
?
7.2
8.6
300
950
mA
mA
m A
m A
REFERENCE VOLTAGE
V ref ? out
V ref ? out
V refLineReg
V refLoadReg
I ref ? out
Reference voltage for external threshold setting @ I out = 5 mA
Reference voltage for external threshold setting @ I out = 5 mA – T J =
25 ° C
Vcc rejection capability, I out = 5 mA ? D V CC = 1 V – T J = 25 ° C
Reference variation with load changes, 1 mA < I ref < 5 mA – T J =
25 ° C
Maximum output current capability
6
6
6
6
6
4.75
4.9
?
?
5
5
5
0.01
1.6
?
5.25
5.1
5
7
?
V
V
mV
mV
mA
NOTE:
DELAY
Maximum capacitance directly connected to V REF pin must be under 100 nF.
t DEL1
t DEL2
Turn ? on LLC delay after PFC OK signal is asserted
Turn ? off LLC after power good pin goes low (Note 3)
?
?
10
2
20
5
30
8
ms
ms
PROTECTIONS
R Pull ? up
t on/off
V on
V off
V op
I PG
V PG
I PGadj
V PGadjH
TSD
TSDhyste
on/off pin pull ? up resistor
Propagation delay from on to off (ML & MU are off) (Note 4)
Low level input voltage on on/off pin (NCP1910 is enabled)
High level input voltage on on/off pin (NCP1910 is disabled)
Open voltage on on/off pin
Maximum Power good pin sink current capability
Power good saturation voltage for I PG = 5 mA
Input bias current, PGadj pin
PG comparator hysteresis
Temperature shutdown (Note 4)
Temperature Hysteresis Shutdown
4
4
4
4
4
3
3
7
7
?
?
?
?
?
3
?
5
?
?
?
140
?
5
?
?
?
7
?
?
10
100
?
30
?
1
1
?
?
?
350
?
?
?
?
k W
m s
V
V
V
mA
mV
nA
mV
° C
° C
POWER FACTOR CORRECTION
GATE DRIVE SECTION
R POH
R POL
t Pr
t Pf
Source Resistance @ I DRV = ? 100 mA
Sink Resistance @ I DRV = 100 mA
Gate Drive Voltage Rise Time from 1.5 V to 10.5 V (C L = 1 nF)
Gate Drive Voltage Fall Time from 10.5 V to 1.5 V (C L = 1 nF)
18
18
18
18
?
?
?
?
9
6.6
60
40
20
18
?
?
W
W
ns
ns
3. In normal operation, when the power supply is un ? plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,
when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge
slope. However, if for an unknown reason the PFC is disabled (fault, short ? circuit), the PG pin immediately opens and if sufficient voltage
is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.
4. Guaranteed by design.
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